1. Field of the Invention
The present invention relates to a control circuit for controlling a power conversion circuit using PWM signals, an inverter apparatus including the control circuit, and an interconnection inverter system including the inverter apparatus.
2. Description of the Related Art
In recent years, distributed power sources employing natural energy such as sunlight have tended to become increasingly prevalent. Interconnection inverter systems that have been developed include an inverter circuit for converting DC power generated by a distributed power source into AC power, and supply the converted AC power to a connected load or power system.
FIG. 48 is a block diagram for describing a general interconnection inverter system A′ for supplying power to a three-phase power system B (hereinafter, abbreviated to “system B”).
The interconnection inverter system A′ includes a DC power source 100, an inverter circuit 200, a filter circuit 300, a transformer circuit 400, and a control circuit 500. The inverter circuit 200 is a three-phase full bridge inverter and converts a DC voltage that has been input from the DC power source 100 into an AC voltage by switching six switching elements between the on state and the off state. The control circuit 500 generates PWM signals for controlling the inverter circuit 200, based on signals input from various types of sensors. The inverter circuit 200 switches the switching elements between the on state and the off state based on the PWM signals input from the control circuit 500. It is this switching that is referred to when “switching” is mentioned hereinafter. The filter circuit 300 removes the high-frequency component resulting from switching from the AC voltage input from the inverter circuit 200. The transformer circuit 400 raises or lowers the AC voltage input from the filter circuit 300 so as to be at substantially the same level as the system voltage of the system B.
The power consumed by the switching of the switching elements is referred to as “switching loss”, and this switching loss lowers the power conversion efficiency of the inverter circuit 200. A method for reducing switching loss has been developed in order to improve power conversion efficiency. For example, a method for reducing switching loss has been developed in which a period for which no pulse is generated is periodically provided in the PWM signals so as to periodically stop the switching.
In this method, so-called NVS (Neutral Voltage Shift) control is performed, which is control in which the neutral point potential of three phases is shifted at a ⅓-cycle interval, and the potential of each phase is fixed at a negative-side potential in each ⅓ cycle, thus stopping the switching in each phase for the period for which the potential is fixed at the negative-side potential. NVS control can reduce the number of times that switching is performed, thus enabling a reduction in switching loss. In this specification, the three phases are respectively referred to as the U phase, the V phase, and the W phase, with the phase of the system voltage in the V phase being delayed by 2π/3 relative to the U phase, and the phase of the system voltage in the W phase being delayed by 4π/3 (advanced by 2π/3) relative to the U phase.
Specifically, NVS control is performed by generating command value signals (hereinafter, referred to as “NVS command value signals”), which have a special waveform that is “0” for ⅓ of the cycle, and controlling the inverter circuit 200 with PWM signals generated based on the NVS command value signals. The NVS command value signals are generated by switching a line voltage command value signal for specifying the waveform of the output line voltage of the interconnection inverter system A′, a signal whose polarity is the inverse that of the line voltage command value signal, and a zero signal having the value “0”. The line voltage command value signal is generated using the difference between phase voltage command value signals for specifying the waveforms of the phase voltages to be output by the interconnection inverter system A′.
FIGS. 49A to 49C are diagrams for describing the waveform of NVS command value signals.
A waveform Xuv shown in FIG. 49A is the waveform of a line voltage command value signal Xuv for specifying the waveform of the U-phase line voltage relative to the V phase. The line voltage command value signal Xuv is a difference signal between a phase voltage command value signal Xu for specifying the waveform of the U-phase phase voltage and a phase voltage command value signal Xv for specifying the waveform of the V-phase phase voltage. Since the amplitude of the phase voltage command value signal Xu is “1”, the amplitude of the line voltage command value signal Xuv is √(3). Also, a waveform Xvw is the waveform of a line voltage command value signal Xvw for specifying the waveform of the V-phase line voltage relative to the W phase. The line voltage command value signal Xvw is a difference signal between the phase voltage command value signal Xv for specifying the waveform of the V-phase phase voltage and a phase voltage command value signal Xw for specifying the waveform of the W-phase phase voltage. Also, a waveform Xwu is the waveform of a line voltage command value signal Xwu for specifying the waveform of the W-phase line voltage relative to the U phase. The line voltage command value signal Xwu is a difference signal between the phase voltage command value signal Xw for specifying the waveform of the W-phase phase voltage and the phase voltage command value signal Xu for specifying the waveform of the U-phase phase voltage. In FIG. 49, the phase of the U-phase phase voltage command value signal Xu is used as the reference for illustration.
A waveform Xvu shown in FIG. 49B is the waveform of a signal Xvu whose polarity is the inverse of that of the line voltage command value signal Xuv. Also, a waveform Xwv is the waveform of a signal Xwv whose polarity is the inverse of that of the line voltage command value signal Xvw, and a waveform Xuw is the waveform of a signal Xuw whose polarity is the inverse of that of the line voltage command value signal Xwu.
A waveform Xu′ shown in FIG. 49C is the waveform of a U-phase NVS command value signal Xu′. The NVS command value signal Xu′ is generated by switching between the line voltage command value signal Xuv, the signal Xuw, and the zero signal. The waveform Xu′ has the waveform Xuv for the period −π/6≤θ≤π/2(=3π/6), the waveform Xuw for the period 3π/6≤θ≤7π/6, and is “0” for the period 7π/6≤θ≤11π/6. Note that the phase of the phase voltage command value signal Xu is θ. Similarly, the waveform Xv′, which is the waveform of the V-phase NVS command value signal Xv′, is “0” for the period −π/6≤θ≤π/2(=3π/6), and has the waveform Xvw for the period 3π/6≤θ≤π/6, and the waveform Xvu for the period 7π/6≤θ≤11π/6. Also, the waveform Xw′, which is the waveform of the W-phase NVS command value signal Xw′, has the waveform Xwv for the period −π/6≤θ≤π/2(=3π/6), is “0” for the period 3π/6≤θ≤7π/6, and has the waveform Xwu for the period 7π/6≤θ≤11π/6. The waveform of the difference signal between the NVS command value signals Xu′ and Xv′ matches the waveform Xuv (see FIG. 49A) of the line voltage command value signal Xuv. Accordingly, the interconnection inverter system A′ can output a line voltage having the same waveform as that of the line voltage command value signal Xuv.
PWM signals for controlling the inverter circuit 200 are generated by comparing the NVS command value signals Xu′, Xv′, and Xw′ with a carrier signal.
FIG. 50 is a diagram for describing a method for generating a U-phase PWM signal from the NVS command value signal Xu′ and a carrier signal. In this figure, the NVS command value signal Xu′ is indicated as waveform X, and the carrier signal is indicated as waveform C. The PWM signal is generated as a pulse signal that is at the high level for the period for which the NVS command value signal Xu′ is higher than the carrier signal, and is at the low level for the period for which the NVS command value signal Xu′ is lower than or equal to the carrier signal. A waveform P1 shown in this figure is the waveform of the U-phase PWM signal generated from the NVS command value signal Xu′ and the carrier signal. The waveform P1 is at the high level for the period for which the waveform X is higher than the waveform C, and is at the low level for the period for which the waveform X is lower than or equal to the waveform C. The U-phase PWM signal is input to the U-phase positive-side switching elements to control the switching thereof. On the other hand, a PWM signal (see a waveform P4 shown in FIG. 50) whose polarity is the inverse of that of the U-phase PWM signal is input to the U-phase negative-side switching elements to control the switching thereof. Note that V-phase and W-phase PWM signals are also generated in a similar manner.
As shown by the waveform P1 in FIG. 50, the U-phase PWM signal (waveform P1) is continuously at the low level for the period for which the NVS command value signal Xu′ (waveform X) is “0”, and therefore the switching of the switching elements stops in this period. Accordingly, the number of times that the switching elements are switched is cut down to ⅔, thus enabling a reduction in switching loss.